Renesas HD6417641 用户手册

Section 6   Power-Down Modes 

Rev. 4.00  Sep. 14, 2005  Page 168 of 982 

REJ09B0023-0400 

 

2 

MSTP5 

0 

R/W 

Module Stop 5 

When the MSTP5 bit is set to 1, the supply of the 
clock to the cache memory is halted. 

0: The cache memory runs. 

1: Clock supply to the cache memory halted. 

1 

MSTP4 

0 

R/W 

Module Stop 4 

When the MSTP4 bit is set to 1, the supply of the 
clock to the U memory is halted. 

0: The U memory runs. 

1: Clock supply to the U memory halted. 

0 

MSTP3 

0 

R/W 

Module Stop 3 

When the MSTP3 bit is set to 1, the supply of the 
clock to the X/Y memory is halted. 

0: The X/Y memory runs. 

1: Clock supply to the X/Y memory halted. 

 

STBCR3 is a readable/writable 8-bit register used to select whether or not individual modules 
operate in power-down mode. STBCR3 is initialized (to H'00) by a power-on reset, but retains its 
previous value after a manual reset or a period in the standby mode. Only byte access is valid. 

7 

HIZ 

0 

R/W 

Port High Impedance 

This bit selects whether the state of a specified pin is 
retained or the pin is placed in the high-impedance 
state. See Appendix A, Pin States to determine the 
pin to which this control is applied. 

Do not set this bit when the TME bit of WTSCR of the 
WDT is 1. When setting the output pin to the high-
impedance state, set the HIZ bit with the TME bit 
being 0. 

0: The pin state is held in standby mode. 

1: The pin state is set to the high-impedance state in 

standby mode.