Renesas HD6417641 用户手册

Section 7   Cache 

Rev. 4.00  Sep. 14, 2005  Page 182 of 982 

REJ09B0023-0400 

 

The cache has the following registers. 

•  Cache control register 1 (CCR1) 
•  Cache control register 2 (CCR2) 

 

The cache is enabled or disabled using the CE bit in CCR1. CCR1 also has the CF bit (which 
invalidates all cache entries), and the WT and WB bits (which select either write-through mode or 
write-back mode). Programs that change the contents of CCR1 should be placed in an address 
space that is not cached. When updating the contents of CCR1, bits 31 to 4 must always be cleared 
to 0. 

CCR1 is initialized to H'00000000 by a power-on or manual reset and retain the previous value by 
standby mode, module standby mode, and sleep mode. 

31 to 4 

 All 

0 

R 

Reserved 

These bits are always read as 0. The write value 
should always be 0. 

3 CF  0 R/W 

Cache 

Flush 

Writing 1 flushes all cache entries (clears the V, U, 
and LRU bits of all cache entries to 0). Always reads 
0. Write-back to external memory is not performed 
when the cache is flushed. 

2 WB  0 R/W 

Write 

Back 

Switches write-back/write-through the cache's 
operating mode for area P1. 

0: Write-through mode 

1: Write-back mode  

1 WT  0 R/W 

Write 

Through 

Indicates the cache's operating mode for areas P0 and 
P3. 

0: Write-back mode 

1: Write-through mode