Renesas HD6417641 用户手册
Section 9 Exception Handling
Rev. 4.00 Sep. 14, 2005 Page 201 of 982
REJ09B0023-0400
The above operations from 1 to 3 are executed in sequence. During these operations, no other
exceptions may be accepted. By changing the SPT and SSR before executing the RTE instruction,
a status different from that in effect before the exception handling can also be specified.
exceptions may be accepted. By changing the SPT and SSR before executing the RTE instruction,
a status different from that in effect before the exception handling can also be specified.
Note: For details on the CPU processing mode in which RTE delay slot instructions are
executed, please refer to section 9.6, Usage Notes.
9.2.2 Exception
Vector
Addresses
A vector address for general exceptions is determined by adding a vector offset to a vector base
address. The vector offset for general exceptions other than the TLB error exception is
H'00000100. The vector offset for interrupts is H'00000600. The vector base address is loaded into
the vector base register (VBR) using the software.
address. The vector offset for general exceptions other than the TLB error exception is
H'00000100. The vector offset for interrupts is H'00000600. The vector base address is loaded into
the vector base register (VBR) using the software.
9.2.3 Exception
Codes
The exception codes are written to bits 11 to 0 of the EXPEVT register (for reset or general
exceptions) or the INTEVT2 register (for interrupt requests) to identify each specific exception
event. See section 10, Interrupt Controller (INTC), for details of the exception codes for interrupt
requests. Table 9.1 lists exception codes for resets and general exceptions.
exceptions) or the INTEVT2 register (for interrupt requests) to identify each specific exception
event. See section 10, Interrupt Controller (INTC), for details of the exception codes for interrupt
requests. Table 9.1 lists exception codes for resets and general exceptions.
9.2.4
Exception Request and BL Bit (Multiple Exception Prevention)
The BL bit in SR is set to 1 when a reset or exception is accepted. While the BL bit is set to 1,
acceptance of general exceptions is restricted as described below, making it possible to effectively
prevent multiple exceptions from being accepted.
acceptance of general exceptions is restricted as described below, making it possible to effectively
prevent multiple exceptions from being accepted.
If the BL bit is set to 1, an interrupt request is not accepted and is retained. The interrupt request is
accepted when the BL bit is cleared to 0. If the CPU is in low power consumption mode, an
interrupt is accepted even if the BL bit is set to 1 and the CPU returns from the low power
consumption mode.
accepted when the BL bit is cleared to 0. If the CPU is in low power consumption mode, an
interrupt is accepted even if the BL bit is set to 1 and the CPU returns from the low power
consumption mode.
A DMA error is not accepted and is retained if the BL bit is set to 1 and accepted when the BL bit
is cleared to 0. User break requests generated while the BL bit is set are ignored and are not
retained. Accordingly, user breaks are not accepted even if the BL bit is cleared to 0.
is cleared to 0. User break requests generated while the BL bit is set are ignored and are not
retained. Accordingly, user breaks are not accepted even if the BL bit is cleared to 0.
If a general exception other than a DMA address error or user break occurs while the BL bit is set
to 1, the CPU enters a state similar to that in effect immediately after a reset, and passes control to
the reset vector (H'A0000000) (multiple exception). In this case, unlike a normal reset, modules
to 1, the CPU enters a state similar to that in effect immediately after a reset, and passes control to
the reset vector (H'A0000000) (multiple exception). In this case, unlike a normal reset, modules