Renesas HD6417641 用户手册
Section 11 User Break Controller (UBC)
Rev. 4.00 Sep. 14, 2005 Page 243 of 982
REJ09B0023-0400
11.2 Register
Descriptions
The user break controller has the following registers. For details on register addresses and access
sizes, refer to section 24, List of Registers.
sizes, refer to section 24, List of Registers.
• Break address register A (BARA)
• Break address mask register A (BAMRA)
• Break bus cycle register A (BBRA)
• Break address register B (BARB)
• Break address mask register B (BAMRB)
• Break bus cycle register B (BBRB)
• Break data register B (BDRB)
• Break data mask register B (BDMRB)
• Break control register (BRCR)
• Execution times break register (BETR)
• Branch source register (BRSR)
• Branch destination register (BRDR)
• Break address mask register A (BAMRA)
• Break bus cycle register A (BBRA)
• Break address register B (BARB)
• Break address mask register B (BAMRB)
• Break bus cycle register B (BBRB)
• Break data register B (BDRB)
• Break data mask register B (BDMRB)
• Break control register (BRCR)
• Execution times break register (BETR)
• Branch source register (BRSR)
• Branch destination register (BRDR)
11.2.1 Break
Address
Register A (BARA)
BARA is a 32-bit readable/writable register. BARA specifies the address used as a break condition
in channel A.
in channel A.
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
31 to 0
BAA31 to
BAA0
BAA0
All 0
R/W
Break Address A
Store the address on the LAB or IAB specifying break
conditions of channel A.
conditions of channel A.