Renesas HD6417641 用户手册

Section 11 User Break Controller (UBC)

Rev. 4.00 Sep. 14, 2005 Page 246 of 982

REJ09B0023-0400

11.2.4 Break

Address Register B (BARB)

BARB is a 32-bit readable/writable register. BARB specifies the address used as a break condition
in channel B. Control bits CDB1, CDB0, XYE, and XYS in BBRB select one of the four address
buses for break condition B.

Bit Bit

Name

Initial
Value R/W Description

31 to 0

BAB31 to
BAB0

All 0

R/W

Break Address B

Store an address which specifies a break condition in
channel B.

If the I bus or L bus is selected in BBRB, an IAB or
LAB address is set in BAB31 to BAB0.

If the X memory is selected in BBRB, the values in
bits 15 to 1 in XAB are set in BAB31 to BAB17. In this
case, the values in BAB16 to BAB0 are arbitrary.

If the Y memory is selected in BBRB, the values in
bits 15 to 1 in YAB are set in BAB15 to BAB1. In this
case, the values in BAB31 to BAB16 are arbitrary.

Table 11.1 Specifying Break Address Register

Bus Selection in
BBRB

BAB31 to BAB17

BAB16

BAB15 to BAB1

BAB0

L bus

LAB31 to LAB0

I bus

IAB31 to IAB0

X bus

XAB15 to XAB1

Don't care

Y bus

Don't care

YAB15 to YAB1

Don't care