Renesas HD6417641 用户手册

Section 11   User Break Controller (UBC) 

 

 

Rev. 4.00  Sep. 14, 2005  Page 251 of 982 

 

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BRCR sets the following conditions: 

1.  Channels A and B are used in two independent channel conditions or under the sequential 

condition. 

2.  A break is set before or after instruction execution. 

3.  Specify whether to include the number of execution times on channel B in comparison 

conditions. 

4.  Determine whether to include data bus on channel B in comparison conditions. 

5.  Enable PC trace. 

 

The break control register (BRCR) is a 32-bit readable/writable register that has break conditions 
match flags and bits for setting a variety of break conditions. 

31 to 16 

 All 

0 

R 

Reserved 

These bits are always read as 0. The write value 
should always be 0. 

15 

SCMFCA 

0 

R/W 

L Bus Cycle Condition Match Flag A 

When the L bus cycle condition in the break conditions 
set for channel A is satisfied, this flag is set to 1 (not 
cleared to 0). In order to clear this flag, write 0 into this 
bit. 

0: The L bus cycle condition for channel A does not 

match 

1: The L bus cycle condition for channel A matches 

14 

SCMFCB 

0 

R/W 

L Bus Cycle Condition Match Flag B 

When the L bus cycle condition in the break conditions 
set for channel B is satisfied, this flag is set to 1 (not 
cleared to 0). In order to clear this flag, write 0 into this 
bit. 

0: The L bus cycle condition for channel B does not 

match 

1: The L bus cycle condition for channel B matches