Renesas HD6417641 用户手册

Section 12   Bus State Controller (BSC) 

Rev. 4.00  Sep. 14, 2005  Page 272 of 982 

REJ09B0023-0400 

 

Table 12.1 shows pin configuration of the BSC. 

A25 to A0 

Output  Address bus 

D31 to D0 

I/O 

Data bus 

BS 

Output  Bus cycle start 

CS0, CS2 to CS4 Output Chip 

select 

CS5A Output 

Chip 

select 

Active only for address map 1 

RD/

WR Output 

Read/write 

Connects to 

WE pins when SDRAM or byte-selection SRAM is 

connected. 

RD 

Output  Read pulse signal (read data output enable signal) 

WE3/ICIOWR/AH  Output  Indicates that D31 to D24 are being written to. 

Connected to the byte select signal when a byte-selection SRAM is 
connected. 

Functions as the address hold signal when the MPX-IO is used. 

Functions as the selection signals for D31 to D24 when SDRAM is 
connected. 

WE2/ICIRD 

Output  Indicates that D23 to D16 are being written to.  

Connected to the byte select signal when a byte-selection SRAM is 
connected. 

Functions as the selection signals for D23 to D16 when SDRAM is 
connected. 

WE1/WE 

Output  Indicates that D15 to D8 are being written to.  

Connected to the byte select signal when a byte-selection SRAM is 
connected. 

Functions as the selection signals for D15 to D8 when SDRAM is 
connected.