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Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 329 of 982
REJ09B0023-0400
12.5.3
Access Wait Control
Wait cycle insertion on a normal space access can be controlled by the settings of bits WR3 to
WR0 in CSnWCR. It is possible for areas 4, 5A, and 5B to insert wait cycles independently in
read access and in write access. The areas other than 4, 5A, and 5B have common access wait for
read cycle and write cycle. The specified number of Tw cycles are inserted as wait cycles in a
normal space access shown in figure 12.9.
WR0 in CSnWCR. It is possible for areas 4, 5A, and 5B to insert wait cycles independently in
read access and in write access. The areas other than 4, 5A, and 5B have common access wait for
read cycle and write cycle. The specified number of Tw cycles are inserted as wait cycles in a
normal space access shown in figure 12.9.
T1
CKIO
A25 to A0
CSn
RD/
WR
RD
D31 to D0
WEn
D31 to D0
BS
Tw
Read
Write
T2
DACKn*
Note: * The waveform for
DACKn is when active low is specified.
Figure 12.9 Wait Timing for Normal Space Access (Software Wait Only)