Renesas HD6417641 用户手册
Rev. 4.00 Sep. 14, 2005 Page iv of l
General Precautions on Handling of Product
1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note: Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a pass-
through current flows internally, and a malfunction may occur.
are in their open states, intermediate levels are induced by noise in the vicinity, a pass-
through current flows internally, and a malfunction may occur.
3. Processing before Initialization
Note: When power is first supplied, the product's state is undefined.
The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.
4. Prohibition of Access to Undefined or Reserved Addresses
Note: Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system's
operation is not guaranteed if they are accessed.
may have been be allocated to these addresses. Do not access these registers; the system's
operation is not guaranteed if they are accessed.
5. Treatment of Power Supply (0 V) Pins
Note: There should be no voltage difference between the system ground pins (0 V power
supply), VssQ, Vss, Vss, Vss (PLL1), and Vss (PLL2).
If voltage difference is created between the system ground pins, malfunctions may occur or
excessive current flows during standby due to through current. Voltage difference should not
be created between the system ground pins, VssQ, Vss, Vss (PLL1), and Vss (PLL2).
excessive current flows during standby due to through current. Voltage difference should not
be created between the system ground pins, VssQ, Vss, Vss (PLL1), and Vss (PLL2).