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Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 376 of 982
REJ09B0023-0400
12.5.7
Burst ROM (Clock Asynchronous) Interface
The burst ROM (clock asynchronous) interface is used to access a memory with a high-speed read
function using a method of address switching called the burst mode or page mode. In a burst ROM
(clock asynchronous) interface, basically the same access as the normal space is performed, but
the 2nd and subsequent accesses are performed only by changing the address, without negating the
RD signal at the end of the 1st cycle. In the 2nd and subsequent accesses, addresses are changed at
the falling edge of the CKIO.
function using a method of address switching called the burst mode or page mode. In a burst ROM
(clock asynchronous) interface, basically the same access as the normal space is performed, but
the 2nd and subsequent accesses are performed only by changing the address, without negating the
RD signal at the end of the 1st cycle. In the 2nd and subsequent accesses, addresses are changed at
the falling edge of the CKIO.
For the 1st access cycle, the number of wait cycles specified by the W3 to W0 bits in the
CSnWCR register is inserted. For the 2nd and subsequent access cycles, the number of wait cycles
specified by the W1 to W0 bits in the CSnWCR register is inserted.
CSnWCR register is inserted. For the 2nd and subsequent access cycles, the number of wait cycles
specified by the W1 to W0 bits in the CSnWCR register is inserted.
In the access to the burst ROM (clock asynchronous), the
BS signal is asserted only to the first
access cycle. An external wait input is valid only to the first access cycle. In the single access or
write access that do not perform the burst operation in the page flash ROM interface, access
timing is same as a normal space. Table 12.17 lists a relationship between bus width, access size,
and the number of bursts. Figure 12.36 shows a timing chart.
write access that do not perform the burst operation in the page flash ROM interface, access
timing is same as a normal space. Table 12.17 lists a relationship between bus width, access size,
and the number of bursts. Figure 12.36 shows a timing chart.
Table 12.17 Relationship between Bus Width, Access Size, and Number of Bursts
Bus Width
CSnWCR. BEN Bit
Access Size
Number of Bursts Number of Accesses
8 bits
Not affected
8 bits
1
1
Not affected
16 bits
2
1
Not affected
32 bits
4
1
0
16
bytes
16
1
1
4
4
16 bits
Not affected
8 bits
1
1
Not affected
16 bits
1
1
Not affected
32 bits
2
1
0
16
bytes
8
1
1
2
4
32 bits
Not affected
8 bits
1
1
Not affected
16 bits
1
1
Not affected
32 bits
1
1
Not affected
16 bytes
4
1