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Section 13 Direct Memory Access Controller (DMAC)
Rev. 4.00 Sep. 14, 2005 Page 426 of 982
REJ09B0023-0400
13.4.2
DMA Transfer Requests
DMA transfer requests are basically generated in either the data transfer source or destination, but
they can also be generated by devices and on-chip peripheral modules that are neither the source
nor the destination. Transfers can be requested in three modes: auto request, external request, and
on-chip module request. The request mode is selected in the RS3 to RS0 bits of the DMA channel
control registers 0 to 3 (CHCR_0 to CHCR_3), and the DMA extension resource selectors 0 and 1
(DMARS0, DMARS1).
they can also be generated by devices and on-chip peripheral modules that are neither the source
nor the destination. Transfers can be requested in three modes: auto request, external request, and
on-chip module request. The request mode is selected in the RS3 to RS0 bits of the DMA channel
control registers 0 to 3 (CHCR_0 to CHCR_3), and the DMA extension resource selectors 0 and 1
(DMARS0, DMARS1).
Auto-Request Mode: When there is no transfer request signal from an external source, as in a
memory-to-memory transfer or a transfer between memory and an on-chip peripheral module
unable to request a transfer, the auto-request mode allows the DMAC to automatically generate a
transfer request signal internally. When the DE bits of CHCR_0 to CHCR_3 and the DME bit of
the DMAOR are set to 1, the transfer begins so long as the TE bits of CHCR_0 to CHCR_3 and
the NMIF bit of DMAOR are all 0.
memory-to-memory transfer or a transfer between memory and an on-chip peripheral module
unable to request a transfer, the auto-request mode allows the DMAC to automatically generate a
transfer request signal internally. When the DE bits of CHCR_0 to CHCR_3 and the DME bit of
the DMAOR are set to 1, the transfer begins so long as the TE bits of CHCR_0 to CHCR_3 and
the NMIF bit of DMAOR are all 0.
External Request Mode: In this mode a transfer is performed at the request signals (
DREQ0 to
DREQ1) of an external device. This is valid for DMA channels 0 to 1. Choose one of the modes
shown in table 13.4 according to the application system. When this mode is selected, if the DMA
transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0), a transfer is performed upon a
request at the
shown in table 13.4 according to the application system. When this mode is selected, if the DMA
transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0), a transfer is performed upon a
request at the
DREQ input.
Table 13.4 Selecting External Request Modes with the RS Bits
RS3 RS2 RS1 RS0 Address
Mode
Source
Destination
0 0 0 0 Dual
address
mode
Any
Any
0 External
memory,
memory-mapped
external device
external device
External device with
DACK
0 0 1
1
Single address mode
External device with
DACK
External memory,
memory-mapped
external device
memory-mapped
external device
Choose to detect
DREQ by either the falling edge or low level of the signal input with the DREQ
level (DL) bit and DS bit of CHCR_0 and CHCR_1 as shown in table 13.5. The source of the
transfer request does not have to be the data transfer source or destination.
transfer request does not have to be the data transfer source or destination.