Renesas HD6417641 用户手册
Section 13 Direct Memory Access Controller (DMAC)
Rev. 4.00 Sep. 14, 2005 Page 445 of 982
REJ09B0023-0400
• When an address error occurs during a read cycle:
Neither read cycles nor write cycles are generated; only the transfer request is cleared.
However, when the transfer-request source was an on-chip peripheral module (MTU),
use whichever of the following methods is appropriate to clear the transfer request.
However, when the transfer-request source was an on-chip peripheral module (MTU),
use whichever of the following methods is appropriate to clear the transfer request.
a. When the TC bit of CHCR is 1: Clear the corresponding flag to resume a transfer after
address-error exception processing. In this case, the transfer on the corresponding
channel resumes when the DE bit is set to 1. If you do not want transfer to resume on a
channel, perform a dummy transfer on that channel to clear the transfer request; do this
by setting 1 in TCR and dummy addresses in the SAR and DAR.
channel resumes when the DE bit is set to 1. If you do not want transfer to resume on a
channel, perform a dummy transfer on that channel to clear the transfer request; do this
by setting 1 in TCR and dummy addresses in the SAR and DAR.
b. When the TC bit of CHCR is 0: Use software to clear the transfer-request flag of the
MTU.
• When an address error occurs during a write cycle:
Only read cycles are generated and the transfer request is cleared. However, when the
transfer-request source is the on-chip peripheral module (MTU) and the TC bit of
CHCRn is set to 1, clear the transfer request by software, in the same way as when an
address error occurs during a read cycle, described above.
transfer-request source is the on-chip peripheral module (MTU) and the TC bit of
CHCRn is set to 1, clear the transfer request by software, in the same way as when an
address error occurs during a read cycle, described above.
B. Completion of transfer by clearing DME of DMAOR to 0
When the DME bit of DMAOR is cleared to 0, DMA transfer on all channels is forcibly
suspended after the current transfer has been completed. If the suspended transfer was the
final transfer, TE is set to 1 and the transfer is then completed.
suspended after the current transfer has been completed. If the suspended transfer was the
final transfer, TE is set to 1 and the transfer is then completed.
13.4.7 Notes
on
Usage
1. Clear the DE bit for the corresponding channel before changing the value in the channel
control register (CHCR) for that channel of the DMAC.
2. Do not place the system in software standby mode during DMA transfer and do not select
module standby mode by setting the module standby bit of the DMAC. Clear the DE bits of all
channels before any transition to the software standby mode or module standby mode.
channels before any transition to the software standby mode or module standby mode.
3. Ensure that the system is in the normal operating state for the execution of any DMA transfer
where locations in the U memory or X/Y memory are selected as the sources or destinations of
the data. While the DMAC can operate in sleep mode, the U memory and X/Y memory are in
the operation-stopped state. Accordingly, access from the DMAC is not possible.
the data. While the DMAC can operate in sleep mode, the U memory and X/Y memory are in
the operation-stopped state. Accordingly, access from the DMAC is not possible.
4. The same internal request cannot be set for multiple channels.
5. The transfer request should be implemented after the settings of registers in DMAC have been
completed.