Renesas HD6417641 用户手册

Section 15   User Debugging Interface (H-UDI) 

 

 

Rev. 4.00  Sep. 14, 2005  Page 457 of 982 

 

 REJ09B0023-0400 

The H-UDI has the following registers. Refer the section 24, List of Registers, for the addresses 
and access size for these registers. 

•  Bypass register (SDBPR) 
•  Instruction register (SDIR) 
•  Boundary scan register (SDBSR) 
•  ID register (SDID) 

 

SDBPR is a 1-bit register that cannot be accessed by the CPU. When SDIR is set to the bypass 
mode, SDBPR is connected between H-UDI pins TDI and TDO. The initial value is undefined but 
is initialized to 0 if the TAP is in Capture-DR state. 

SDIR is a 16-bit read-only register. The register is in JTAG IDCODE in its initial state. It is 
initialized by 

TRST assertion or in the TAP test-logic-reset state, and can be written to by the H-

UDI irrespective of the CPU mode. Operation is not guaranteed if a reserved command is set in 
this register. 

15 to 13 

TI7 to TI5 

All 1 

R 

12 TI4 

0  R 

11 to 8 

TI3 to TI0 

All 1 

R 

Test Instruction 7 to 0 

The H-UDI instruction is transferred to SDIR by a 
serial input from TDI. 

For commands, see table 15.2. 

7 to 2 

 All 

1 

R 

Reserved 

These bits are always read as 1. 

1 

 0 

R 

Reserved 

This bit is always read as 0. 

0 

 1 

R 

Reserved 

This bit is always read as 1.