Renesas HD6417641 用户手册

Section 16   I

2

C Bus Interface 2 (IIC2) 

Rev. 4.00  Sep. 14, 2005  Page 480 of 982 

REJ09B0023-0400 

 

4 

SDAOP 

1 

R/W 

SDAO Write Protect 

This bit controls change of output level of the SDA pin 
by modifying the SDAO bit. To change the output level, 
clear SDAO and SDAOP to 0 or set SDAO to 1 and 
clear SDAOP to 0. This bit is always read as 1. 

3 

SCLO 

1 

R 

This bit monitors SCL output level. When SCLO is 1, 
SCL pin outputs high. When SCLO is 0, SCL pin 
outputs low. 

2 

 1 

 Reserved 

This bit is always read as 1, and cannot be modified. 

1 

IICRST 

0 

R/W 

IIC Control Part Reset 

This bit resets the control part except for I

2

C registers. If 

this bit is set to 1 when hang-up occurs because of 
communication failure during I

2

C operation, I

2

C control 

part can be reset without setting ports and initializing 
registers.  

0 

 1 

 Reserved 

This bit is always read as 1, and cannot be modified. 

 

ICMR is an 8-bit readable/writable register that selects whether the MSB or LSB is transferred 
first, performs master mode wait control, and selects the transfer bit count. 

ICMR is initialized to H'38 by a power-on reset. 

7 MLS 0 R/W 

MSB-First/LSB-First 

Select 

0: MSB-first 

1: LSB-first 

Set this bit to 0 when the I

2

C bus format is used. 

6 

 0 

 Reserved 

The write value should always be 0.