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Section 18   Multi-Function Timer Pulse Unit (MTU) 

 

 

Rev. 4.00  Sep. 14, 2005  Page 581 of 982 

 

 REJ09B0023-0400 

In phase counting mode, the phase difference between two external clock inputs is detected and 
TCNT counts up or down accordingly. This mode can be set for channels 1 and 2. 

When phase counting mode is set, an external clock is selected as the counter input clock and 
TCNT operates as an up/down-counter regardless of the setting of bits TPSC0 to TPSC2 and bits 
CKEG0 and CKEG1 in TCR. However, the functions of bits CCLR0 and CCLR1 in TCR, and of 
TIOR, TIER, and TGR, are valid, and input capture/compare match and interrupt functions can be 
used. 

This can be used for two-phase encoder pulse input. 

If overflow occurs when TCNT is counting up, the TCFV flag in TSR is set; if underflow occurs 
when TCNT is counting down, the TCFU flag is set. 

The TCFD bit in TSR is the count direction flag. Reading the TCFD flag reveals whether TCNT is 
counting up or down. 

Table 18.32 shows the correspondence between external clock pins and channels. 

 

When channel 1 is set to phase counting mode 

TCLKA 

TCLKB 

When channel 2 is set to phase counting mode 

TCLKC 

TCLKD