Renesas HD6417641 用户手册

下载
页码 1036
Section 19   Serial Communication Interface with FIFO (SCIF) 
 
 
Rev. 4.00  Sep. 14, 2005  Page 699 of 982 
 
 REJ09B0023-0400 
19.3.7 
Serial Status Register (SCFSR) 
The serial status register (SCFSR) is a 16-bit register.  The upper 8 bits indicate the number of 
receives errors in the SCFRDR data, and the lower 8 bits indicate the status flag indicating SCIF 
operating state. 
The CPU can always read and write to SCFSR, but cannot write 1 to the status flags (ER, TEND, 
TDFE, BRK, RDF, and DR). These flags can be cleared to 0 only if they have first been read 
(after being set to 1). Bits 3 (FER) and 2 (PER) are read-only bits that cannot be written. SCFSR is 
initialized to H'0060 by a power-on reset. 
Bit Bit 
Name 
Initial 
value R/W Description 
15 
14 
13 
12 
PER3 
PER2 
PER1 
PER0 
Number of Parity Errors 
Indicate the quantity of data including a parity error in 
the receive data stored in the receive FIFO data 
register (SCFRDR).  The value indicated by bits 15 to 
12 represents the number of parity errors in SCFRDR. 
When parity errors have occurred in all 16-byte 
receive data in SCFRDR, PER3 to PER0 show 0. 
11 
10 
FER3 
FER2 
FER1 
FER0 
Number of Framing Errors 
Indicate the quantity of data including a framing error 
in the receive data stored in SCFRDR.  The value 
indicated by bits 11 to 8 represents the number of 
framing errors in SCFRDR.  When framing errors 
have occurred in all 16-byte receive data in SCFRDR, 
FER3 to FER0 show 0.