Renesas HD6417641 用户手册
Section 19 Serial Communication Interface with FIFO (SCIF)
Rev. 4.00 Sep. 14, 2005 Page 707 of 982
REJ09B0023-0400
19.3.8
Bit Rate Register (SCBRR)
The bit rate register (SCBRR) is an 8-bit register that, together with the baud rate generator clock
source selected by the CKS1 and CKS0 bits in the serial mode register (SCSMR), determines the
serial transmit/receive bit rate.
source selected by the CKS1 and CKS0 bits in the serial mode register (SCSMR), determines the
serial transmit/receive bit rate.
The CPU can always read and write to SCBRR. SCBRR is initialized to H'FF by a power-on reset.
Each channel has independent baud rate generator control, so different values can be set in three
channels.
Each channel has independent baud rate generator control, so different values can be set in three
channels.
The SCBRR setting is calculated as follows:
• Asynchronous mode:
N =
× 10
6
- 1
64
× 2
2n-1
× B
P
φ
• Synchronous mode:
N =
× 10
6
- 1
8
× 2
2n-1
× B
P
φ
B: Bit rate (bits/s)
N: SCBRR setting for baud rate generator (0
N: SCBRR setting for baud rate generator (0
≤ N ≤ 255)
P
φ: Operating frequency for peripheral modules (MHz)
n:
Baud rate generator clock source (n
= 0, 1, 2, 3) (for the clock sources and values of
n, see table 19.2.)
Table 19.2 SCSMR Settings
SCSMR
Settings
n Clock
Source
CKS1
CKS0
0 P
φ 0 0
1 P
φ/4 0
1
2 P
φ/16 1
0
3 P
φ/64 1
1
Note: The bit rate error in asynchronous is given by the following formula:
Error (%) =
- 1
× 100
(N + 1)
× B × 64
2n-1
× 2
P
φ × 10
6