Renesas HD6417641 用户手册
Section 19 Serial Communication Interface with FIFO (SCIF)
Rev. 4.00 Sep. 14, 2005 Page 714 of 982
REJ09B0023-0400
19.3.9
FIFO Control Register (SCFCR)
The FIFO control register (SCFCR) resets the quantity of data in the transmit and receive FIFO
registers, sets the trigger data quantity, and contains an enable bit for loop-back testing. SCFCR
can always be read and written to by the CPU. It is initialized to H'0000 by a power-on reset.
registers, sets the trigger data quantity, and contains an enable bit for loop-back testing. SCFCR
can always be read and written to by the CPU. It is initialized to H'0000 by a power-on reset.
Bit Bit
Name
Initial
value R/W
value R/W
Description
15 to 11 —
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
always be 0.
10
9
8
RSTRG2
RSTRG1
RSTRG0
0
0
0
R/W
R/W
R/W
RTS Output Active Trigger
When the quantity of receive data in receive FIFO
register (SCFRDR) becomes more than the number
shown below,
register (SCFRDR) becomes more than the number
shown below,
RTS signal is set to high.
000: 15
001: 1
010: 4
011: 6
100: 8
101: 10
110: 12
111: 14
Note:
Set the trigger number to 1 when the receive
data is transferred by the DMAC in
synchronous mode. If the set trigger number is
other than 1, the receive data remains in
SCFRDR should be read by the CPU.
data is transferred by the DMAC in
synchronous mode. If the set trigger number is
other than 1, the receive data remains in
SCFRDR should be read by the CPU.