Renesas HD6417641 用户手册

Section 20   USB Function Module 

 

 

Rev. 4.00  Sep. 14, 2005  Page 751 of 982 

 

 REJ09B0023-0400 

2 EP0oTS 

0  R/W 

EP0o 

Receive 

Complete 

This bit is set to 1 when endpoint 0 receives data from 
the host normally, stores the data in the FIFO buffer, 
and returns an ACK handshake to the host. 

1 EP0iTR 

0  R/W 

EP0i 

Transfer 

Request 

This bit is set if there is no valid transmit data in the 
FIFO buffer when an IN token for endpoint 0 is 
received from the host. A NACK handshake is 
returned to the host until data is written to the FIFO 
buffer and packet transmission is enabled. 

0 

EP0iTS 

0 

R/W 

EP0i Transmit Complete 

This bit is set when data is transmitted to the host 
from endpoint 0 and an ACK handshake is returned. 

 

Together with USB interrupt flag registers 0 (USBIFR0) and 2 (USBIFR2), USBIFR1 indicates 
interrupt status information required by the application. When an interrupt occurs, the 
corresponding bit is set to 1 and an interrupt request is sent to the CPU according to the 
combination with USB interrupt enable register 1 (USBIER1). Clearing is performed by writing 0 
to the bit to be cleared, and 1 to the other bits. However, VBUSMN is a status bit, and cannot be 
cleared. 

USBIFR1 is initialized to H'20 by a power-on reset. 

7 to 4 

 All 

0 

R 

Reserved 

The write value should always be 0. 

3 

VBUSMN 

0 

R 

Status bit for monitoring the status of the VBUS pin. 
The status of the VBUS pin is reflected. 

0: Disconnected 

1: Connected