Renesas HD6417641 用户手册
Section 25 Electrical Characteristics
Rev. 4.00 Sep. 14, 2005 Page 934 of 982
REJ09B0023-0400
25.3.6
Burst ROM Read Cycle
T1
t
AD1
t
RSD
t
RDS3
t
RSD
t
CSD1
t
AS
Tw
Twx
T2B
Twb
T2B
t
AD2
t
AD2
t
CSD1
CKIO
A25 to A0
CSn
RD/
WR
D31 to D0
WEn
BS
RD
WAIT
Note: * Waveform for
DACKn and TENDn when active low is selected.
DACKn,
TENDn*
t
AD1
t
BSD
t
DACD
t
DACD
t
BSD
t
RWD1
t
WTS1
t
WTS1
t
RWD1
t
RDH3
t
RDH3
t
WTH1
t
WTH1
t
RDS3
Figure 25.22 Burst ROM Read Cycle
(One Software Wait Cycle, One Asynchronous External Burst Wait Cycle, Two Burst)