Renesas H8S/2111B 用户手册
Rev. 1.00, 05/04, page 69 of 544
5.3 Register
Descriptions
The interrupt controller has the following registers. For details on the system control register
(SYSCR), refer to section 3.2.2, System Control Register (SYSCR).
(SYSCR), refer to section 3.2.2, System Control Register (SYSCR).
• Interrupt control registers A to C (ICRA to ICRC)
• Address break control register (ABRKCR)
• Break address registers A to C (BARA to BARC)
• IRQ sense control registers (ISCRH, ISCRL)
• IRQ enable register (IER)
• IRQ status register (ISR)
• Keyboard matrix interrupt mask registers (KMIMRA, KMIMR)
• Wake-up event interrupt mask register (WUEMRB)
• Address break control register (ABRKCR)
• Break address registers A to C (BARA to BARC)
• IRQ sense control registers (ISCRH, ISCRL)
• IRQ enable register (IER)
• IRQ status register (ISR)
• Keyboard matrix interrupt mask registers (KMIMRA, KMIMR)
• Wake-up event interrupt mask register (WUEMRB)
5.3.1 Interrupt
Control
Registers A to C (ICRA to ICRC)
The ICR registers set interrupt control levels for interrupts other than NMI and address breaks.
The correspondence between interrupt sources and ICRA to ICRC settings is shown in table 5.2.
Bit Bit
Name
Initial
Value
Value
R/W Description
7 to 0
ICRn7 to
IRCn0
IRCn0
All 0
R/W
Interrupt Control Level
0: Corresponding interrupt source is interrupt control
level 0 (no priority)
level 0 (no priority)
1: Corresponding interrupt source is interrupt control
level 1 (priority)
level 1 (priority)
[Legend]
n:
n:
A to C