Renesas H8S/2111B 用户手册
Rev. 1.00, 05/04, page 125 of 544
7.10 Port
A
Port A is an 8-bit I/O port. Port A pins also function as keyboard buffer controller I/O pins, and
key-sense interrupt input pins. Port A input/output operates by VccB power independent from the
Vcc power. Up to 5 V can be applied to port A pins if VccB power is 5 V. Port A has the
following registers. PADDR and PAPIN have the same address.
key-sense interrupt input pins. Port A input/output operates by VccB power independent from the
Vcc power. Up to 5 V can be applied to port A pins if VccB power is 5 V. Port A has the
following registers. PADDR and PAPIN have the same address.
• Port A data direction register (PADDR)
• Port A output data register (PAODR)
• Port A input data register (PAPIN)
• Port A output data register (PAODR)
• Port A input data register (PAPIN)
7.10.1
Port A Data Direction Register (PADDR)
PADDR specifies input or output for the pins of port A on a bit-by-bit basis.
Bit Bit
Name
Initial
Value
Value
R/W Description
7 PA7DDR
0
W
6 PA6DDR
0
W
5 PA5DDR
0
W
4 PA4DDR
0
W
3 PA3DDR
0
W
2 PA2DDR
0
W
1 PA1DDR
0
W
0 PA0DDR
0
W
The corresponding port A pins are output ports when
PADDR bits are set to 1, and input ports when
cleared to 0.
PADDR bits are set to 1, and input ports when
cleared to 0.
PA7 to PA2 pins are used as the keyboard buffer
controller I/O pins by setting the KBIOE bit to 1, while
the I/O direction according to PA7DDR to PA2DDR is
ignored.
controller I/O pins by setting the KBIOE bit to 1, while
the I/O direction according to PA7DDR to PA2DDR is
ignored.
PADDR has the same address as PAPIN, if read, port
A state is returned.
A state is returned.
7.10.2
Port A Output Data Register (PAODR)
PAODR stores output data for port A.
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
7 PA7ODR
0
R/W
6 PA6ODR
0
R/W
5 PA5ODR
0
R/W
4 PA4ODR
0
R/W
3 PA3ODR
0
R/W
2 PA2ODR
0
R/W
1 PA1ODR
0
R/W
0 PA0ODR
0
R/W
PAODR can always be read or written to, regardless
of the contents of PADDR.
of the contents of PADDR.