Renesas H8S/2111B 用户手册
Rev. 1.00, 05/04, page 136 of 544
7.13
Ports E, F
Ports E and F are two sets of 8-bit I/O ports. Port F also functions as I/O pins for TMR_X*,
TMR_Y*, TMR_A, and TMR_B. Ports E and F have the following registers.
TMR_Y*, TMR_A, and TMR_B. Ports E and F have the following registers.
• Port E data direction register (PEDDR)
• Port E output data register (PEODR)
• Port E input data register (PEPIN)
• Port E Nch-OD control register (PENOCR)
• Port F data direction register (PFDDR)
• Port F output data register (PFODR)
• Port F input data register (PFPIN)
• Port F Nch-OD control register (PFNOCR)
• Port E output data register (PEODR)
• Port E input data register (PEPIN)
• Port E Nch-OD control register (PENOCR)
• Port F data direction register (PFDDR)
• Port F output data register (PFODR)
• Port F input data register (PFPIN)
• Port F Nch-OD control register (PFNOCR)
Note: *
The program development tool (emulator) does not support this function.
7.13.1
Port E and Port F Data Direction Registers (PEDDR, PFDDR)
PEDDR and PFDDR select input or output for the pins of port E and port F on a bit-by-bit basis.
Bit Bit
Name
Initial
Value
Value
R/W Description
7 PE7DDR
0
W
6 PE6DDR
0
W
5 PE5DDR
0
W
4 PE4DDR
0
W
3 PE3DDR
0
W
2 PE2DDR
0
W
1 PE1DDR
0
W
0 PE0DDR
0
W
0: Port E pin is an input pin
1: Port E pin is an output pin
PEDDR has the same address as PEPIN, and if read,
the port E pin states will be returned.
the port E pin states will be returned.
Bit Bit
Name
Initial
Value R/W
Value R/W
Description
7 PF7DDR
0
W
6 PF6DDR
0
W
5 PF5DDR
0
W
4 PF4DDR
0
W
3 PF3DDR
0
W
2 PF2DDR
0
W
1 PF1DDR
0
W
0 PF0DDR
0
W
0: Port F pin is an input pin
1: Port F pin is an output pin
PFDDR has the same address as PFPIN, and if read,
the port F pin states will be returned.
the port F pin states will be returned.