Renesas H8S/2111B 用户手册
Rev. 1.00, 05/04, page 151 of 544
8.3.2
PWM Data Registers 7 to 0 (PWDR7 to PWD0)
PWDR are 8-bit readable/writable registers. The PWM has eight PWM data registers. Each
PWDR specifies the duty cycle of the basic pulse to be output, and the number of additional
pulses. The value set in PWDR corresponds to a 0 or 1 ratio in the conversion period. The upper
four bits specify the duty cycle of the basic pulse as 0/16 to 15/16 with a resolution of 1/16. The
lower four bits specify how many extra pulses are to be added within the conversion period
comprising 16 basic pulses. Thus, a specification of 0/256 to 255/256 is possible for 0/1 ratios
within the conversion period. For 256/256 (100%) output, port output should be used.
PWDR specifies the duty cycle of the basic pulse to be output, and the number of additional
pulses. The value set in PWDR corresponds to a 0 or 1 ratio in the conversion period. The upper
four bits specify the duty cycle of the basic pulse as 0/16 to 15/16 with a resolution of 1/16. The
lower four bits specify how many extra pulses are to be added within the conversion period
comprising 16 basic pulses. Thus, a specification of 0/256 to 255/256 is possible for 0/1 ratios
within the conversion period. For 256/256 (100%) output, port output should be used.
8.3.3
PWM Data Polarity Register A (PWDPRA)
PWDPRA selects the PWM output phase.
Bit
Bit
Name
Name
Initial
Value
Value
R/W Description
7
6
5
4
3
2
1
0
OS7
OS6
OS5
OS4
OS3
OS2
OS1
OS0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Output Select 7 to 0
These bits select the PWM output phase. Bits OS7 to
OS0 correspond to outputs PW7 to PW0.
OS0 correspond to outputs PW7 to PW0.
0: PWM direct output (PWDR value corresponds to high
width of output)
1: PWM inverted output (PWDR value corresponds to
low width of output)