Renesas H8S/2111B 用户手册
Rev. 1.00, 05/04, page 172 of 544
9.5.4
Input Capture Input Timing
The rising or falling edge can be selected for the input capture input timing by the IEDGA to
IEDGD bits in TCR. Figure 9.7 shows the usual input capture timing when the rising edge is
selected.
IEDGD bits in TCR. Figure 9.7 shows the usual input capture timing when the rising edge is
selected.
φ
Input capture
input pin
input pin
Input capture signal
Figure 9.7 Input Capture Input Signal Timing (Usual Case)
If ICRA to ICRAD are read when the corresponding input capture signal arrives, the internal input
capture signal is delayed by one system clock (
capture signal is delayed by one system clock (
φ). Figure 9.8 shows the timing for this case.
T
1
T
2
Read cycle of ICRA to ICRD
φ
Input capture
input pin
input pin
Input capture signal
Figure 9.8 Input Capture Input Signal Timing (When ICRA to ICRD are Read)