Renesas H8S/2111B 用户手册
Rev. 1.00, 05/04, page 217 of 544
10.10.3 Conflict
between
TCOR Write and Compare-Match
If a compare-match occurs during the T
2
state of a TCOR write cycle as shown in figure 10.16, the
TCOR write takes priority and the compare-match signal is disabled. With TMR_X, and TMR_A,
a TICR input capture conflicts with a compare-match in the same way as with a write to TCORC.
In this case also, the input capture takes priority and the compare-match signal is disabled.
a TICR input capture conflicts with a compare-match in the same way as with a write to TCORC.
In this case also, the input capture takes priority and the compare-match signal is disabled.
φ
Address
TCOR address
Internal write signal
TCNT
TCOR
N
M
TCOR write cycle by CPU
TCOR write data
N
N + 1
Compare-match signal
Disabled
Note: * TMR_A,
TMR_B
T
1
T
2
T
3
*
Figure 10.16 Conflict between TCOR Write and Compare-Match
10.10.4 Conflict between Compare-Matches A and B
If compare-matches A and B occur at the same time, the operation follows the output status that is
defined for compare-match A or B, according to the priority of the timer output shown in table
10.8.
defined for compare-match A or B, according to the priority of the timer output shown in table
10.8.
Table 10.8 Timer Output Priorities
Output Setting
Priority
Toggle output
High
1 output
0 output
No change
Low