Renesas H8S/2111B 用户手册

Rev. 1.00, 05/04, page 237 of 544 

 

The SCI has the following registers. 

•  Receive shift register (RSR) 
•  Receive data register (RDR) 
•  Transmit data register (TDR) 
•  Transmit shift register (TSR) 
•  Serial mode register (SMR) 
•  Serial control register (SCR) 
•  Serial status register (SSR) 
•  Serial interface mode register (SCMR) 
•  Bit rate register (BRR) 
•  Serial pin select register (SPSR)* 

 

Note:  *  The program development tool (emulator) does not support this function. 

RSR is a shift register used to receive serial data that converts it into parallel data. When one 
frame of data has been received, it is transferred to RDR automatically. RSR cannot be directly 
accessed by the CPU. 

RDR is an 8-bit register that stores receive data. When the SCI has received one frame of serial 
data, it transfers the received serial data from RSR to RDR where it is stored. After this, RSR can 
receive the next data. Since RSR and RDR function as a double buffer in this way, continuous 
receive operations can be performed. After confirming that the RDRF bit in SSR is set to 1, read 
RDR for only once. RDR cannot be written to by the CPU. RDR is initialized to H'00. 

TDR is an 8-bit register that stores transmit data. When the SCI detects that TSR is empty, it 
transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered 
structures of TDR and TSR enables continuous serial transmission. If the next transmit data has 
already been written to TDR when one frame of data is transmitted, the SCI transfers the written 
data to TSR to continue transmission. Although TDR can be read from or written to by the CPU at 
all times, to achieve reliable serial transmission, write transmit data to TDR for only once after 
confirming that the TDRE bit in SSR is set to 1. TDR is initialized to H'FF.