Renesas H8S/2111B 用户手册
Rev. 1.00, 05/04, page 272 of 544
12.8 Usage
Notes
12.8.1 Module
Stop Mode Setting
SCI operation can be disabled or enabled using the module stop control register. The initial setting
is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For
details, refer to section 20, Power-Down Modes.
is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For
details, refer to section 20, Power-Down Modes.
12.8.2
Break Detection and Processing
When framing error detection is performed, a break can be detected by reading the RxD pin value
directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag in SSR is set,
and the PER flag may also be set. Note that, since the SCI continues the receive operation even
after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again.
directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag in SSR is set,
and the PER flag may also be set. Note that, since the SCI continues the receive operation even
after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again.
12.8.3
Mark State and Break Detection
When the TE bit in SCR is 0, the TxD pin is used as an I/O port whose direction (input or output)
and level are determined by DR and DDR of the port. This can be used to set the TxD pin to the
mark state (high level) or send a break during serial data transmission. To maintain the
communication line at mark state until TE is set to 1, set both DDR and DR to 1. Since the TE bit
is cleared to 0 at this point, the TxD pin becomes an I/O port, and 1 is output from the TxD pin. To
send a break during serial transmission, first set DDR to 1 and DR to 0, and then clear the TE bit
to 0. When the TE bit is cleared to 0, the transmitter is initialized regardless of the current
transmission state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin.
and level are determined by DR and DDR of the port. This can be used to set the TxD pin to the
mark state (high level) or send a break during serial data transmission. To maintain the
communication line at mark state until TE is set to 1, set both DDR and DR to 1. Since the TE bit
is cleared to 0 at this point, the TxD pin becomes an I/O port, and 1 is output from the TxD pin. To
send a break during serial transmission, first set DDR to 1 and DR to 0, and then clear the TE bit
to 0. When the TE bit is cleared to 0, the transmitter is initialized regardless of the current
transmission state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin.
12.8.4
Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
Transmission cannot be started when a receive error flag (ORER, FER, or RER) is SSR is set to 1,
even if the TDRE flag in SSR is cleared to 0. Be sure to clear the receive error flags to 0 before
starting transmission. Note also that the receive error flags cannot be cleared to 0 even if the RE
bit in SCR is cleared to 0.
even if the TDRE flag in SSR is cleared to 0. Be sure to clear the receive error flags to 0 before
starting transmission. Note also that the receive error flags cannot be cleared to 0 even if the RE
bit in SCR is cleared to 0.
12.8.5
Relation between Writing to TDR and TDRE Flag
Data can be written to TDR irrespective of the TDRE flag status in SSR. However, if the new
data is written to TDR when the TDRE flag is 0, that is, when the previous data has not been
transferred to TSR yet, the previous data in TDR is lost. Be sure to write transmit data to TDR
after verifying that the TDRE flag is set to 1.
data is written to TDR when the TDRE flag is 0, that is, when the previous data has not been
transferred to TSR yet, the previous data in TDR is lost. Be sure to write transmit data to TDR
after verifying that the TDRE flag is set to 1.