Renesas H8S/2111B 用户手册
Rev. 1.00, 05/04, page 334 of 544
13.4.8 Noise
Canceller
The logic levels at the SCL and SDA pins are routed through noise cancellers before being latched
internally. Figure 13.28 shows a block diagram of the noise canceller.
internally. Figure 13.28 shows a block diagram of the noise canceller.
The noise canceller consists of two cascaded latches and a match detector. The SCL (or SDA) pin
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
System clock
cycle
Sampling clock
C
D
Q
Latch
C
D
Q
Latch
SCL or
SDA input signal
SDA input signal
Match
detector
Internal SCL or
SDA signal
SDA signal
Sampling
clock
clock
Figure 13.28 Block Diagram of Noise Canceler