Renesas H8S/2111B 用户手册
Rev. 1.00, 05/04, page 337 of 544
13.6 Usage
Notes
1. In master mode, if an instruction to generate a start condition is issued and then an instruction
to generate a stop condition is issued before the start condition is output to the I
2
C bus, neither
condition will be output correctly. To output the start condition followed by the stop condition,
after issuing the instruction that generates the start condition, read DR in each I
after issuing the instruction that generates the start condition, read DR in each I
2
C bus output
pin, and check that SCL and SDA are both low. The pin states can be monitored by reading
DR even if the ICE bit is set to 1. Then issue the instruction that generates the stop condition.
Note that SCL may not yet have gone low when BBSY is cleared to 0.
DR even if the ICE bit is set to 1. Then issue the instruction that generates the stop condition.
Note that SCL may not yet have gone low when BBSY is cleared to 0.
2. Either of the following two conditions will start the next transfer. Pay attention to these
conditions when accessing to ICDR.
Write to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from ICDRT to
Write to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from ICDRT to
ICDRS)
Read from ICDR when ICE = 1 and TRS = 0 (including automatic transfer from ICDRS to
ICDRR)
3. Table 13.8 shows the timing of SCL and SDA outputs in synchronization with the internal
clock. Timings on the bus are determined by the rise and fall times of signals affected by the
bus load capacitance, series resistance, and parallel resistance.
bus load capacitance, series resistance, and parallel resistance.
Table 13.8 I
2
C Bus Timing (SCL and SDA Outputs)
Item
Symbol Output
Timing
Unit Notes
SCL output cycle time
t
SCLO
28t
cyc
to 256t
cyc
ns
SCL output high pulse width
t
SCLHO
0.5t
SCLO
ns
SCL output low pulse width
t
SCLLO
0.5t
SCLO
ns
SDA output bus free time
t
BUFO
0.5t
SCLO
– 1t
cyc
ns
Start condition output hold time
t
STAHO
0.5t
SCLO
– 1t
cyc
ns
Retransmission start condition output
setup time
setup time
t
STASO
1t
SCLO
ns
Stop condition output setup time
t
STOSO
0.5t
SCLO
+ 2t
cyc
ns
Data output setup time (master)
1t
SCLLO
– 3t
cyc
Data output setup time (slave)
t
SDASO
1t
SCLL
– (6t
cyc
or 12t
cyc
*)
ns
Data output hold time
t
SDAHO
3t
cyc
ns
See figure
22.22.
Note: * 6t
cyc
when IICX is 0, 12t
cyc
when 1.
4. SCL and SDA inputs are sampled in synchronization with the internal clock. The AC timing
therefore depends on the system clock cycle t
cyc
, as shown in section 22, Electrical
Characteristics. Note that the I
2
C bus interface AC timing specifications will not be met with a
system clock frequency of less than 5 MHz.