Renesas H8S/2111B 用户手册
Rev. 1.00, 05/04, page 356 of 544
1
2
3
KCLK
(pin state)
(pin state)
KD
(pin state)
(pin state)
KCLK
(input)
(input)
KCLK
(output)
(output)
KB7 to KB0
PER
KBS
KBF
Start
bit
bit
Parity bit Stop bit
Receive processing/
error handling
error handling
Automatic I/O inhibit
Previous data
Receive data
Flag cleared
9
10
11
7
0
1
KB0
KB1
[1] [2] [3]
[4] [5]
[6]
Figure 14.4 Receive Timing
14.4.2 Transmit
Operation
In a transmit operation, KCLK (clock) is an output on the keyboard side, and KD (data) is an
output on the chip (system) side. KD outputs a start bit, 8 data bits (LSB-first), an odd parity bit,
and a stop bit, in that order. The KD value is valid when KCLK is high. A sample transmit
processing flowchart is shown in figure 14.5, and the transmit timing in figure 14.6.
output on the chip (system) side. KD outputs a start bit, 8 data bits (LSB-first), an odd parity bit,
and a stop bit, in that order. The KD value is valid when KCLK is high. A sample transmit
processing flowchart is shown in figure 14.5, and the transmit timing in figure 14.6.