Renesas H8S/2111B 用户手册
Rev. 1.00, 05/04, page 422 of 544
Table 16.3 A/D Conversion Time (Single Mode)
CKS = 0
CKS = 1
Item
Symbol
Min. Typ. Max. Min. Typ. Max.
A/D conversion start delay
time
time
t
D
10 — 17 6 — 9
Input sampling time
t
SPL
— 63 — — 31 —
A/D conversion time
t
CONV
259 — 266 131 — 134
Note: * Values in the table indicate the number of states.
16.4.4 External
Trigger Input Timing
A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to B'11 in
ADCR, external trigger input is enabled at the
ADCR, external trigger input is enabled at the
ADTRG pin. A falling edge at the ADTRG pin sets
the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan
modes, are the same as when the ADST bit has been set to 1 by software. Figure 16.4 shows the
timing.
modes, are the same as when the ADST bit has been set to 1 by software. Figure 16.4 shows the
timing.
A/D conversion
φ
ADTRG
Internal trigger
signal
ADST
Figure 16.4 External Trigger Input Timing