Renesas H8S/2111B 用户手册

Rev. 1.00, 05/04, page 46 of 544 

 

The H8S/2000 CPU has four main processing states: the reset state, exception handling state, 
program execution state, and program stop state. Figure 2.13 indicates the state transitions. 

•  Reset state 

In this state the CPU and on-chip peripheral modules are all initialized and stopped. When the 
RES input goes low, all current processing stops and the CPU enters the reset state. All 
interrupts are masked in the reset state. Reset exception handling starts when the 

RES signal 

changes from low to high. For details, refer to section 4, Exception Handling. 

The reset state can also be entered by a watchdog timer overflow. 

•  Exception-handling state 

The exception-handling state is a transient state that occurs when the CPU alters the normal 
processing flow due to an exception source, such as, a reset, trace, interrupt, or trap instruction. 
The CPU fetches a start address (vector) from the exception vector table and branches to that 
address. For further details, refer to section 4, Exception Handling. 

•  Program execution state 

In this state the CPU executes program instructions in sequence.  

•  Program stop state 

This is a power-down state in which the CPU stops operating. The program stop state occurs 
when a SLEEP instruction is executed or the CPU enters hardware standby mode. For details, 
refer to section 20, Power-Down Modes.