Renesas SH7781 用户手册
21. Serial Communication Interface with FIFO (SCIF)
Rev.1.00 Jan. 10, 2008 Page 1062 of 1658
REJ09B0261-0100
REJ09B0261-0100
21.3.9
FIFO Control Register n (SCFCR)
SCFCR is a register that performs data count resetting and trigger data number setting for transmit
and receive FIFO registers, and also contains a loopback test enable bit.
and receive FIFO registers, and also contains a loopback test enable bit.
SCFCR can always be read from and written to by the CPU.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
14
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LOOP
RFCL
TFCL
MCE*
1
TTRG0
TTRG1
RTRG0
RTRG1
RST
RG2*
1
RST
RG1*
1
RST
RG0*
1
⎯
⎯
⎯
⎯
⎯
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
BIt:
Initial value:
R/W:
Bit Bit
Name
Initial
Value R/W
Value R/W
Description
15 to 11 —
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
should always be 0.
10
9
8
RSTRG2*
1
RSTRG1*
1
RSTRG0*
1
0
0
0
R/W
R/W
R/W
SCIF_RTS Output Active Trigger
The
The
SCIF_RTS signal becomes high when the number
of receive data stored in SCFRDR exceeds the trigger
setting count shown below.
setting count shown below.
000:63
001:1
010:8
011:16
100:32
101:48
110:54
111:60
7
6
RTRG1
RTRG0
0
0
R/W
R/W
Receive FIFO Data Count Trigger
These bits are used to set the number of receive data
bytes that sets the RDF flag in SCFSR.
bytes that sets the RDF flag in SCFSR.
The RDF flag is set when the number of receive data
bytes in SCFRDR is equal to or greater than the trigger
setting count shown below.
bytes in SCFRDR is equal to or greater than the trigger
setting count shown below.
00:1
01:16
10:32
11:48