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21.   Serial Communication Interface with FIFO (SCIF) 
Rev.1.00  Jan. 10, 2008  Page 1070 of 1658 
REJ09B0261-0100 
 
21.3.14
  Serial Error Register n (SCRER) 
SCRER is a 16-bit register that indicates the number of receive errors in the data in SCFRDR. 
SCRER can always be read from the CPU. 
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
14
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FER0
FER1
FER2
FER3
FER4
FER5
PER0
PER1
PER2
PER3
PER4
PER5
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
BIt:
Initial value:
R/W:
 
 
Bit Bit 
Name 
Initial 
Value R/W 
Description 
15, 14 
— 
All 0 
Reserved 
These bits are always read as 0. The write value 
should always be 0. 
13 
12 
11 
10 
PER5 
PER4 
PER3 
PER2 
PER1 
PER0 
Number of Parity Errors 
These bits indicate the number of data bytes in which a 
parity error occurred in the receive data stored in 
SCFRDR. 
After the ER bit in SCFSR is set, the value indicated by 
bits PER5 to PER0 is the number of data bytes in 
which a parity error occurred. 
If all 64 bytes of receive data in SCFRDR have parity 
errors, the value indicated by bits PER5 to PER0 is 0. 
7, 6 
— 
All 0 
Reserved 
These bits are always read as 0. The write value 
should always be 0. 
FER5 
FER4 
FER3 
FER2 
FER1 
FER0 
Number of Framing Errors 
These bits indicate the number of data bytes in which a 
framing error occurred in the receive data stored in 
SCFRDR. 
After the ER bit in SCFSR is set, the value indicated by 
bits FER5 to FER0 is the number of data bytes in which 
a framing error occurred. 
If all 64 bytes of receive data in SCFRDR have framing 
errors, the value indicated by bits FER5 to FER0 is 0.