Renesas SH7781 用户手册
22. Serial I/O with FIFO (SIOF)
Rev.1.00 Jan. 10, 2008 Page 1131 of 1658
REJ09B0261-0100
SIOF_SCK
SIOF_SYNC
SIOF_TXD
SIOF_RXD
(a) Falling-edge sampling (REDG = 0)
SIOF_SCK
SIOF_SYNC
SIOF_TXD
SIOF_RXD
(b) Rising-edge sampling (REDG = 1)
Receive timing
Transmit timing
Transmit timing
Receive timing
Transmit timing
Transmit timing
Figure 22.4 SIOF Transmit/Receive Timing
22.4.3
Transfer Data Format
The SIOF performs the following transfer.
• Transmit/receive data: Transfer of 8-bit data/16-bit data/16-bit stereo data
• Control data: Transfer of 16-bit data (uses the transmit/receive control register as interface)
• Control data: Transfer of 16-bit data (uses the transmit/receive control register as interface)
(1)
Transfer Mode
As shown in table 22.6, the SIOF supports the following four transfer modes. The transfer mode
can be specified by the TRMD1 and TRMD0 bits in SIMDR.
can be specified by the TRMD1 and TRMD0 bits in SIMDR.
Table 22.6 Serial Transfer Modes
TRMD1 and
TRMD0
TRMD0
Transfer Mode
SIOF_SYNC
Bit Delay
Control Data*
00
Slave mode 1
Synchronous pulse
Slot position
01
Slave mode 2
Synchronous pulse
Secondary FS
10
Master mode 1
Synchronous pulse
SYNCDL bit
Slot position
11
Master mode 2
L/R
No
Not supported
Note: * The control data method is valid when the FL bits are set to B'1xxx (x: don't care).