Renesas SH7781 用户手册

23.   Serial Peripheral Interface (HSPI) 

Rev.1.00  Jan. 10, 2008  Page 1165 of 1658 

REJ09B0261-0100 

 

Figure 23.2 shows the flow of a transmit/receive operation procedure. 

Yes

No

No

Yes

Start

Reset the system

Select master or slave 

operation by setting the MASL bit 

in SPSCR

Select required interrupts by 

setting TFIE and ROIE bits in 

SPSCR

Check if 

SPTBR is empty by 

reading the TXFL bit 

in SPSR

Write data to SPTBR

TX/RX data to/from slave

Another 

transmit required?

End

 

Depending on the settings of SPCR, the master transmits data to the slave on either the falling or 
rising edge of HSPI_CLK and samples data from the slave at the opposite edge. The data transfer 
between the master and slave is completed when the transmit complete status flag (TXFN) in 
SPSR is set to 1. This flag should be used to identify when an HSPI transfer event (byte 
transmitted and byte received) has occurred, even in the case where the HSPI module is used to 
receive data only (null data being transmitted). By default data is transmitted MSB first, but LSB 
first is also possible depending on how the LMSB bit in SPSCR is set. 

During the transmit operation the slave responds by sending data to the master synchronized with 
the HSPI_CLK from the master transmitted. Data from the slave is sampled and transferred to the 
shift register in the module and on completion of the transmit operation, is transferred to SPRBR.