Renesas SH7781 用户手册

23.   Serial Peripheral Interface (HSPI) 

Rev.1.00  Jan. 10, 2008  Page 1166 of 1658 
REJ09B0261-0100 

 

The 

HSPI_CS pin should be used to select the HSPI module and prepare it to receive data from an 

external master when the HSPI is configured as a slave. When the FBS bit in SPCR is 0, the 
HSPI_CS pin must be driven high between successive bytes (the HSPI_CS pin must be driven 
high after a byte transfer). When FBS = 1, the 

HSPI_CS pin can stay low for several byte 

transmissions. In this case, if the system is configured such that FBS is always 1, the 

HSPI_CS 

line can be fixed at ground (if the HSPI will only be used as a slave). 

In order to reduce the interrupt overhead on the CPU, FIFO mode has been provided. When FIFO 
mode is enabled, up to eight bytes can be written in advance for transmission and up to eight bytes 
can be received before the receive FIFO needs to be read. To transfer the specified amount of data 
between the HSPI module and an external device, use the following procedure: 

1.  Set up the module for the required HSPI transfer characteristics (master/slave, clock polarity 

etc.) and enable FIFO mode. 

2.  Write bytes into the transmit FIFO via SPTBR. If more than eight bytes are to be transmitted, 

enable the transmit FIFO halfway interrupt to keep track of the FIFO level as data is 
transmitted. 

3.  Respond to the transmit FIFO halfway interrupt when it occurs by writing more data to the 

transmit FIFO and reading data from the receive FIFO via SPRBR. 

4.  When all of the transmit data has been written into the transmit FIFO, disable the transmit 

FIFO halfway interrupt and read the contents of the receive FIFO until it is empty. Enable the 
receive FIFO not empty interrupt to keep track of when the final bytes of the transfer are 
received. 

5.  Respond to the receive FIFO not empty interrupt until all the expected data has been received. 

6.  Disable the module until it is required again. 

 

In some applications, an undefined amount of data will be received from an external HSPI device. 
If this is the case, use the following procedure: 

1.  Set up the module for the required HSPI transfer characteristics (master/slave, clock polarity, 

etc.) and enable FIFO mode. 

2.  Fill the transmit FIFO with the data to transmit. Enable the receive FIFO not empty interrupt. 

3.  Respond to the receive FIFO not empty interrupt and read data from the receive FIFO until it is 

empty. Write more data to the transmit FIFO if required. 

4.  Disable the module when the transfer is to stop.