Renesas SH7781 用户手册
24. Multimedia Card Interface (MMCIF)
Rev.1.00 Jan. 10, 2008 Page 1187 of 1658
REJ09B0261-0100
24.3.6
Interrupt Status Registers 0 to 2 (INTSTR0 to INTSTR2)
The INTSTR registers enable or disable MMCIF interrupts FSTAT, TRAN, ERR and FRDY, and
interrupt flags.
interrupt flags.
(1)
INTSTR0
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R/W
FEI
FFI
DRPI
DTI
CRPI CMDI DBSYI
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BTI
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
Interrupt
output
output
7
FEI
0
R/W
FIFO Empty Interrupt Flag
0: No interrupt
[Clearing condition]
Write 0 after reading FEI = 1.
(Writing 1 is invalid)
1: Interrupt requested
[Setting condition]
When FIFO becomes empty while FEIE = 1
and data is being transmitted
and data is being transmitted
(when the FIFO_EMPTY bit in CSTR is set)
FSTAT
6
FFI
0
R/W
FIFO Full Interrupt Flag
0: No interrupt
[Clearing condition]
Write 0 after reading FFI = 1.
(Writing 1 is invalid)
1: Interrupt requested
[Setting condition]
When FIFO becomes full while FFIE = 1
and data is being received
and data is being received
(when the FIFO_FULL bit in CSTR is set)
FSTAT