Renesas SH7781 用户手册
24. Multimedia Card Interface (MMCIF)
Rev.1.00 Jan. 10, 2008 Page 1194 of 1658
REJ09B0261-0100
REJ09B0261-0100
24.3.8
Command Timeout Control Register (CTOCR)
CTOCR specifies the period to generate a timeout for the command response.
The counter (CTOUTC), to which the peripheral bus does not have access, counts the transfer
clock to monitor the command timeout. The initial value of CTOUTC is 0, and CTOUTC starts
counting the transfer clock from the start of command transmission. CTOUTC is cleared and stops
counting the transfer clock when command response reception has been completed, or when the
command sequence has been aborted by setting the CMDOFF bit to 1.
clock to monitor the command timeout. The initial value of CTOUTC is 0, and CTOUTC starts
counting the transfer clock from the start of command transmission. CTOUTC is cleared and stops
counting the transfer clock when command response reception has been completed, or when the
command sequence has been aborted by setting the CMDOFF bit to 1.
When the command response cannot be received, CTOUTC continues counting the transfer clock,
and enters the command timeout error state when the number of transfer clock cycles reaches the
number specified in CTOCR. When the CTERIE bit in INTCR1 is set to 1, the CTERI flag in
INTSTR1 is set. As CTOUTC continues counting transfer clock, the CTERI flag setting condition
is repeatedly generated. To perform command timeout error handling, the command sequence
should be aborted by setting the CMDOFF bit to 1, and then the CTERI flag should be cleared to
prevent extra-interrupt generation.
and enters the command timeout error state when the number of transfer clock cycles reaches the
number specified in CTOCR. When the CTERIE bit in INTCR1 is set to 1, the CTERI flag in
INTSTR1 is set. As CTOUTC continues counting transfer clock, the CTERI flag setting condition
is repeatedly generated. To perform command timeout error handling, the command sequence
should be aborted by setting the CMDOFF bit to 1, and then the CTERI flag should be cleared to
prevent extra-interrupt generation.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
R
CTSEL0
⎯
R
R
R
R
R
R
R/W
⎯
⎯
⎯
⎯
⎯
⎯
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
7 to 1
—
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
always be 0.
0
CTSEL0
1
R/W
Command Timeout Select
0: 128 transfer clock cycles from command
transmission completion to response reception
completion
completion
1: 256 transfer clock cycles from command
transmission completion to response reception
completion
completion
Transfer clock: MMCCLK
Note: If R2 response (17-byte command response) is requested and CTSEL0 is cleared to 0, a
timeout is generated during response reception. Therefore, set CTSEL0 to 1.