Renesas SH7781 用户手册
24. Multimedia Card Interface (MMCIF)
Rev.1.00 Jan. 10, 2008 Page 1198 of 1658
REJ09B0261-0100
REJ09B0261-0100
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
3 TY3 0 R/W
Type
3
Set this bit to 1 when specifying stream transfer. Bits
TY1 and TY0 should be set to 01 or 10.
TY1 and TY0 should be set to 01 or 10.
The command sequence of the stream transfer
specified by this bit ends when it is aborted by the
CMD12 command.
specified by this bit ends when it is aborted by the
CMD12 command.
2 TY2 0 R/W
Type
2
Set this bit to 1 when specifying a multiple block
transfer. Bits TY1 and TY0 should be set to 01 or 10.
transfer. Bits TY1 and TY0 should be set to 01 or 10.
The command sequence of the multiple block transfer
specified by this bit ends when it is aborted by the
CMD12 command.
specified by this bit ends when it is aborted by the
CMD12 command.
1
0
TY1
TY0
0
0
R/W
R/W
Types 1 and 0
These bits specify the existence and direction of
transfer data.
transfer data.
00: A command without data transfer
01: A command with read data reception
10: A command with write data transmission
11: Setting prohibited
24.3.12
Response Type Register (RSPTYR)
RSPTYR is an 8-bit readable/writable register that specifies command format in conjunction with
CMDTYR. Bits RTY2 to RTY0 specify the number of response bytes, and bits RTY6 to RTY4
specify the additional settings.
CMDTYR. Bits RTY2 to RTY0 specify the number of response bytes, and bits RTY6 to RTY4
specify the additional settings.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R
RTY5 RTY4
RTY2 RTY1 RTY0
R/W
R/W
R/W
R
R/W
R/W
R/W
⎯
⎯
RTY6
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
7
⎯ 0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
always be 0.