Renesas SH7781 用户手册

5.   Exception Handling 

Rev.1.00  Jan. 10, 2008  Page 102 of 1658 
REJ09B0261-0100 

 

The various exception handling operations explained here are exception sources, transition address 
on the occurrence of exception, and processor operation when a transition is made.  

•  Condition: 

Power-on reset request 

•  Operations: 

Exception code H'000 is set in EXPEVT, initialization of the CPU and on-chip peripheral 
module is carried out, and then a branch is made to the reset vector (H'A0000000). For details, 
see the register descriptions in the relevant sections. A power-on reset should be executed 
when power is supplied. 

 

•  Condition: 

Manual reset request 

•  Operations: 

Exception code H'020 is set in EXPEVT, initialization of the CPU and on-chip peripheral 
module is carried out, and then a branch is made to the branch vector (H'A0000000). The 
registers initialized by a power-on reset and manual reset are different. For details, see the 
register descriptions in the relevant sections.  

 

•  Source: SDIR.TI[7:4] = B'0110 (negation) or B'0111 (assertion) 
•  Transition address: H'A0000000 
•  Transition operations: 

Exception code H'000 is set in EXPEVT, initialization of VBR and SR is performed, and a 
branch is made to PC = H'A0000000. 

CPU and on-chip peripheral module initialization is performed. For details, see section 30, 
User Debugging Interface (H-UDI), and the register descriptions in the relevant sections.