Renesas SH7781 用户手册

26.   Serial Sound Interface (SSI) Module 

Rev.1.00  Jan. 10, 2008  Page 1335 of 1658 

REJ09B0261-0100 

 

If an overflow occurs during receive DMA operation, the module must be reactivated.  

The receive buffer of SSI has 32-bit common register to the left channel and right channel. If an 
overflow occurs under the condition of control register (SSICR) data-word length (DWL2 to 0) is 
32-bit and system-word length (SWL2 to 0) is 32-bit, SSI has received the data at right channel 
that should be received at left channel. 

If an overflow occurrence is confirmed through an overflow error interrupt or overflow error status 
flag (the OIRQ bit in SSISR), disable the DMA transfer of the SSI to halt its operation by writing 
0 to the EN bit and DMEN bit in SSICR (then terminate the DMAC setting). And clear the 
overflow status flag by writing 0 to the OIRQ bit, set the DMA again to restart transfer.  

Before setting or activating the SSI module, set the peripheral module select registers and the port 
control registers in terms of the SSI0 and SSI1 channels as described in section 28, General 
Purpose I/O Ports (GPIO). 

When terminating data transmission in slave mode, the WS signal (SSI WS) input should be kept 
the active state until SSICR.IDST becomes 1 after SSICR.EN is cleared to 0 (see next page 
figure). The “active state” means the WS signal is being input high (or low) and low (or high) 
alternately as for each system word cycles (it will become more than five system word cycles after 
EN bit is cleared to 0). 

If the WS signal active state input is stopped before SSICR.IDST becomes 1, the transfer of the 
SSI is not terminated normally and the transfer will be suspended. If SSICR.EN is set to 1 again in 
this state, the transfer is resumed from the suspended state and an unexpected data transfer may 
occur. 

Note that, the normal data transmission of the SSI can be resumed from the first or second WS 
falling edge after the EN bit is set to 1 while the IDST bit is 1.