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Renesas SH7781 用户手册

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27.   NAND Flash Memory Controller (FLCTL) 
Rev.1.00  Jan. 10, 2008  Page 1346 of 1658 
REJ09B0261-0100 
 
27.3.2
 
Command Control Register (FLCMDCR) 
FLCMDCR is a 32-bit readable/writable register that issues a command in command access mode, 
specifies address issue, and specifies destination of data to be input or output. In sector access 
mode, FLCMDCR specifies the number of sector transfers. 
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
ADRMD
SCTCNT[19:16]
ADR
CNT2
CDSRC
DOSR
SELRW DOADR
ADRCNT[1:0]
DOCMD2 DOCMD1
SCTCNT[15:0]
 
 
Bit Bit 
Name 
Initial 
Value R/W Description 
31 ADRCNT2 
0  R/W 
Address 
Issue 
Byte Number Specification 
Specifies the number of bytes issued in the address 
stage. 
0: Issues address as many as the bytes specified in 
ADRCNT1 and ADRCNT0 
1: Issues 5-byte address 
Note: Set ADRCNT1 and ADRCNT0 to 0. 
30 to 27  SCTCNT 
[19:16] 
All 0 
R/W 
Selector Transfer Count Specification [19:16] 
These bits are extended bits of bits SCTCNT[15:0]. 
When bits SCTCNT[19:16] and bits SCTCNT[15:0] are 
put together, these bits operate as a 20-bit counter of 
bits SCTCNT[19:0]. 
26 
ADRMD 
0 
R/W 
Sector Access Address Specification 
This bit is invalid in command access mode. This bit is 
valid only in sector access mode. 
0: The value of the address register is handled as a 
physical sector number. Always use this value in 
sector access. 
1: The value of the address register is output as the 
address of flash memory. 
Note: Clear this bit to 0 in continuous sector access.