Renesas SH7781 用户手册

29.   User Break Controller (UBC) 

Rev.1.00  Jan. 10, 2008  Page 1475 of 1658 

REJ09B0261-0100 

 

6.  While the BL bit in the SR register is 1, no break requests are accepted. However, whether or 

not the condition has been satisfied is determined. When the condition is determined to be 
satisfied, the corresponding condition match flag is set.  

7.  If the sequential break conditions are set, the condition match flag is set every time the match 

conditions are satisfied for each channel. When the conditions have been satisfied for the first 
channel in the sequence but not for the second channel in the sequence, clear the condition 
match flag for the first channel in the sequence in order to release the first channel in the 
sequence from the match state.  

 

1.  If the instruction fetch cycle is set in the match condition setting register (CBR0 or CBR1), the 

instruction fetch cycle is handled as a match condition. To request a break upon satisfying the 
match condition, set the BIE bit in the match operation setting register (CRR0 or CRR1) of the 
corresponding channel. Either before or after executing the instruction can be selected as the 
break timing according to the PCB bit value. If the instruction fetch cycle is specified as a 
match condition, be sure to clear the LSB to 0 in the match address setting register (CAR0 or 
CAR1); otherwise, no break occurs.  

2.  If pre-instruction-execution break is specified for the instruction fetch cycle, the break is 

requested when the instruction is fetched and determined to be executed. Therefore, this 
function cannot be used for the instructions which are fetched through overrun (i.e., the 
instructions fetched during branching or making transition to the interrupt routine but not 
executed). For priorities of pre-instruction-execution break and the other exceptions, refer to 
section 5, Exception Handling. If pre-instruction-execution break is specified for the delayed 
slot of the delayed branch instruction, the break is requested before the delayed branch 
instruction is executed. However, do not specify pre-instruction-execution break for the 
delayed slot of the RTE instruction.  

3.  If post-instruction-execution break is specified for the instruction fetch cycle, the break is 

requested after the instruction which satisfied the match condition has been executed and 
before the next instruction is executed. Similar to pre-instruction-execution break, this function 
cannot be used for the instructions which are fetched through overrun. For priorities of post-
instruction-execution break and the other exceptions, refer to section 5, Exception Handling. If 
post-instruction-execution break is specified for the delayed branch instruction and its delayed 
slot, the break does not occur until the first instruction at the branch destination.  

4.  If the instruction fetch cycle is specified as the channel 1 match condition, the DBE bit of 

match condition setting register CBR1 becomes invalid, the settings of match data setting 
register CDR1 and match data mask setting register CDMR1 are ignored. Therefore, the data 
value cannot be specified for the instruction fetch cycle break.