Renesas SH7781 用户手册

29.   User Break Controller (UBC) 

Rev.1.00  Jan. 10, 2008  Page 1485 of 1658 

REJ09B0261-0100 

 

1.  A desired break may not occur between the time when the instruction for rewriting the UBC 

register is executed and the time when the written value is actually reflected on the register. 

After the UBC register is updated, execute one of the following three methods. 

A.  Read the updated UBC register, and execute a branch using the RTE instruction. 

(It is not necessary that a branch using the RTE instruction is next to a reading UBC 
register.) 

B.  Execute the ICBI instruction for any address (including non-cacheable area). 

(It is not necessary that the ICBI instruction is next to a reading UBC register.) 

C.  Set 0 (initial value) to IRMCR.R1 before updating the UBC register and update with 

following sequence. 

a. Write the UBC register. 

b. Read the UBC register which is updated at 1. 

c. Write the value which is read at 2 to the UBC register. 

 

Note:  When two or more UBC registers are updated, executing these methods at each updating 

the UBC registers is not necessary. At only last updating the UBC register, execute one of 
these methods. 

2.  The PCB bit of the CRR0 and CRR1 registers is valid only when the instruction fetch is 

specified as the match condition.  

3.  If the sequential break conditions are set, the sequential break conditions are satisfied when the 

conditions for the first and second channels in the sequence are satisfied in this order. 
Therefore, if the conditions are set so that the conditions for channels 0 and 1 should be 
satisfied simultaneously for the same bus cycle, the sequential break conditions will not be 
satisfied, causing no break.  

4.  For the SLEEP instruction, do not allow the post-instruction-execution break where the 

instruction fetch cycle is the match condition. For the instructions preceding the SLEEP 
instruction by one to five instructions, do not allow the break where the operand access is the 
match condition.  

5.  If the user break and other exceptions occur for the same instruction, they are determined 

according to the specified priority. For the priority, refer to section 5, Exception Handling. If 
the exception having the higher priority occurs, the user break does not occur.  
⎯  The pre-instruction-execution break is accepted prior to any other exception.