Renesas SH7781 用户手册

30. User Debugging Interface (H-UDI)

Rev.1.00 Jan. 10, 2008 Page 1492 of 1658
REJ09B0261-0100

30.3.1

Instruction Register (SDIR)

SDIR is a 16-bit read-only register that can be read from the CPU. Commands are set via the serial
input pin (TDI). SDIR is initialized by

TRST or in the Test-Logic-Reset state of the TAP. This

register can be written to by the H-UDI, regardless of the CPU mode. Operation is not guaranteed
when a reserved command is set to this register.

Bit:

Initial value:

R/W:

Bit

Bit Name Initial Value R/W Description

15 to 8

0000 1110

Test Instruction Bits 7 to 0

0110 xxxx:  H-UDI reset negate
0111 xxxx:  H-UDI reset assert
101x xxxx:  H-UDI interrupt
0000 1110: Initial state

Other than above: Setting prohibited

7 to 0

⎯ All

1 R

Reserved

These bits are always read as 1.

30.3.2

Interrupt Source Register (SDINT)

SDINT is a 16-bit register that can be read from or written to by the CPU. If the H-UDI interrupt
command (Update-IR) is set to SDIR, the INTREQ bit is set to 1. When an H-UDI interrupt
command is set in SDIR, SDINT is connected between the TDI and TDO pins, and becomes a 32-
bit readable register. In this case, the upper 16 bits are 0 and the lower 16 bits are values specified
in SDINT.

Only 0 can be written to the INTREQ bit by the CPU. While this bit is set to 1, an interrupt request
continues to be generated. Therefore, clear this bit to 0 in an interrupt handler and read this bit
again to confirm that this bit is cleared. This register is initialized by

TRST or in the test-logic-

reset state.

INTREQ

Bit:

Initial value:

R/W:

R/W