Renesas SH7781 用户手册
32. Electrical Characteristics
Rev.1.00 Jan. 10, 2008 Page 1592 of 1658
REJ09B0261-0100
REJ09B0261-0100
32.3.4
DBSC2 Signal Timing
Table 32.9 DBSC2 Signal Timing
Conditions: V
DD-DDR
= 1.7 to 1.9 V, V
ref
= 0.9 V, V
DD
= 1.1 V, T
a
=
−20 to +85/−40 to 85°C,
C
L
= 30 pF, ODT=on), Drive Strength=Normal
Item
Symbol Min.
Max. Unit Figure Notes
MCK output cycle
t
CK
3.33 5.0
ns
MCK output high-level pulse
width
width
t
CH
0.45 0.55
t
MCK
MCK output low-level pulse
width
width
t
CL
0.45
0.55
t
MCK
880 — ps
DDR2-600
Address and control signal
setup time to MCK rising edge
setup time to MCK rising edge
t
IS
1290
DDR2-400
880 — ps
DDR2-600
Address and control signal hold
time to MCK rising edge
time to MCK rising edge
t
IH
1290
DDR2-400
Address and control signal
width
width
t
IPW
0.6 — t
MCK
MCLK-to-MDQS skew time
(Read)
(Read)
t
RDQSDLY
−0.2 1.4 ns
MDQS high-level pulse width
(Read)
(Read)
t
RDQSH
0.35 0.65 t
MCK
MDQS low-level pulse width
(Read)
(Read)
t
RDQSL
0.35 0.65
t
MCK
MDQS preamble (Read)
t
RPRE
0.9 1.1 t
MCK
MDQS postamble (Read)
t
RPST
0.4 0.6 t
MCK
−390 390
DDR2-600
MDQS-to-MDQ skew time
(Read)
(Read)
t
RDQSQ
−590 590
ps
DDR2-400
MDQ signal hold time to DQS
(Read)
(Read)
t
RQH
0.45
× t
MCK
−470
— ps
DDR2-600
0.45
× t
MCK
−630
—
DDR2-400