Renesas SH7781 用户手册
32. Electrical Characteristics
Rev.1.00 Jan. 10, 2008 Page 1613 of 1658
REJ09B0261-0100
32.3.14
MMCIF Module Signal Timing
Table 32.19 MMCIF Module Signal Timing
Item Symbol
Min.
Max.
Unit
Figure
MMCCLK clock cycle time
t
MMcyc
50
— ns
MMCCLK clock high level width
t
MMWH
0.4 × t
Mmcyc
—
ns
MMCCLK clock low level width
t
MMWL
0.4 × t
MMcyc
—
ns
MMCCMD output data delay time
t
MMTCD
—
10 ns
32.56
MMCCMD input data hold time
t
MMRCS
10
—
ns
MMCCMD input data setup time
t
MMRCH
10
—
ns
32.57, 32.58
MMCD output data delay time
t
MMTDD
—
10 ns
32.56
MMCD input data setup time
t
MMRDS
10
—
ns 32.57,
32.58
MMCD input data hold time
t
MMRDH
10
—
ns
Note: t
Mmcyc
is the period of one MMCCLK cycle.
t
MMcyc
t
MMWH
t
MMTDD
t
MMTDD
t
MMTCD
t
MMTCD
t
MMWL
MMCLK
MMCCMD (Output)
MMCDAT (Output)
Figure 32.56 MMCIF Transmission Timing