Renesas SH7781 用户手册
Appendix
Rev.1.00 Jan. 10, 2008 Page 1631 of 1658
REJ09B0261-0100
C. Pin
Functions
C.1 Pin
States
Table C.1
Pin States in Reset, Power-Down State, and Bus-Released State
Reset
Pin Name
(LSI level)
(LSI level)
Pin Name
(Module level)
(Module level)
Related
Module I/O
Module I/O
Power-
on Manual Sleep
on Manual Sleep
Module
Standby
Standby
Bus
Release
Release
A[25:0] A[25:0] LBSC
O
PZ
K
K
⎯
PZ/Z
D[31:24] (default) LBSC
I/O
Z
K
K
⎯
Z
D[31:24]
Port F[7:0]
GPIO
I/O
⎯
K K
⎯
Z
D[23:16] (default) LBSC
I/O
Z
K
K
⎯
Z
D[23:16]
Port G[7:0]
GPIO
I/O
⎯
K K
⎯
Z
D[15:0] D[15:0] LBSC
I/O
Z
K
K
⎯
Z
CS[6:0]
CS[6:0] LBSC
O
H(m)/
PZ(s)
PZ(s)
*
1
K K
⎯
PZ/Z
BACK/BSREQ
(default)
(default)
LBSC I/O
H*
2
K K
⎯
O
BACK/BSREQ
Port M0
GPIO
I/O
⎯
K K
⎯
O
BREQ/BSACK
(default)
(default)
LBSC I/O
PZ K
K
⎯
I
BREQ/BSACK
Port M1
GPIO
I/O
⎯
K K
⎯
I
BS
BS LBSC
O
H(m)/
PZ(s)
PZ(s)
*
1
K K
⎯
PZ/Z
R/
W R/W LBSC
O
H(m)/
PZ(s)
PZ(s)
*
1
K K
⎯
PZ/Z
RD/FRAME
RD/FRAME LBSC
O
H(m)/
PZ(s)
PZ(s)
*
1
K K
⎯
PZ/Z
RDY
RDY LBSC
I
PI
K
K
⎯
I
WE0/REG
WE0/REG LBSC
O
H(m)/
PZ(s)
PZ(s)
*
1
K K
⎯
PZ/Z
WE1
WE1 LBSC
O
H(m)/
PZ(s)
PZ(s)
*
1
K K
⎯
PZ/Z
WE2/IORD
WE2/IORD LBSC
O
H(m)/
PZ(s)
PZ(s)
*
1
K K
⎯
PZ/Z
WE3/IOWR
WE3/IOWR LBSC
O
H(m)/
PZ(s)
PZ(s)
*
1
K K
⎯
PZ/Z